The invention relates generally to semiconductor packaging and, in particular, to underfill materials and methods for removing an underfill material from beneath a chip in relation to removal of the chip from a substrate.
A die or chip includes integrated circuits formed by front-end-of-line processing using the semiconductor material of a wafer, a local interconnect level formed by middle-of-line processing, and stacked metallization levels of an interconnect structure formed by back-end-of-line processing. After the wafer is diced, each chip may be joined with a substrate using, for example, a controlled collapse chip connection or flip chip process. In a flip chip process, reflowed solder bumps establish mechanical and electrical connections between pads in the top metallization level of the interconnect structure and a complementary set of pads on the substrate. The solder bumps can be formed on the pads of the chip using any number of techniques, including electroplating, evaporation, printing, and direct placement. Reflow of the solder bumps establishes solder joints that physically and electrically connect the chip pads with the substrate pads.
Underfill may be applied to fill open space beneath the chip that remains between the solder joints. After curing, the underfill may function to protect the solder joints against various adverse environmental factors and redistribute mechanical stresses arising from shock. The underfill may also prevent the solder joints from shearing during thermal cycles. Coefficient of thermal expansion (CTE) mismatch between the chip and the substrate can cause mechanical stresses as temperature changes are experienced that can lead to solder joint shearing and reliability issues.
Improved underfill materials and methods for removing an underfill material from beneath a chip in relation to removal of the chip from a substrate are needed that improve on existing underfill materials and such removal methods.